1. Field of the Invention
The present invention relates generally to analog circuits. More specifically, the invention relates to a clock buffer circuit design that reduces ringing when the buffer is loaded by providing feed forward compensation in an emitter (source) follower circuit.
2. Relationship to the Art
Emitter follower circuits (also referred to as source follower circuits) are used as buffering stages in bipolar (CMOS) technologies because they behave as a low impedance voltage source and the voltage gain is very close to unity. There is, however a problem associated with emitter/source follower circuits. When such a circuit is connected to a capacitive load, the output tends to oscillate or ring. For this reason, emitter/source follower circuits are most useful for applications such as local buffers where ringing with a capacitive load is not a serious problem since the capacitive load is relatively small.
Emitter/source follower circuits are not as well suited to be used as a clock driver because the capacitive load on a clock driving circuit is significant. In high-speed applications such as clock drivers or data buffers, voltage ringing can cause serious problems, such as jitter, reduced noise margin and data dependent noise. The problem becomes most serious when the capacitive load is not linear, i.e., when the capacitive load varies with the clock level. A number of approaches have been devised for solving the problems caused by ringing. One approach is to use a plurality of distributed buffers driven by a master buffer, so that the master buffer and each of the distributed buffers do not individually see a large enough capacitive load to cause ringing to become a problem. Although this approach prevents problems caused by ringing, it also results in higher power dissipation and increased delay.
Another approach to reducing ringing in emitter/source follower circuits caused by capacitive load is to add a resistor in series with the load to damp the oscillation. Adding a resistor to the load, however, causes other problems. As a result of the series resistor, the output may have slower rising/falling edges for transitions.
Other possible approaches such as increasing the follower load current or reducing the source driving impedance have the disadvantage of increasing power consumption. Furthermore, such approaches do not adequately solve the ringing problem.
Another approach has been proposed in "Design Considerations for Very High Speed Si-Bipolar IC's operating up to 50 Gb/s" by H. -M. Rein and M. Moller in IEEE Journal of Solid State Circuits, Vol.31 No. 8, August 1996, which is herein incorporated by reference for all purposes. The approach disclosed attempts to solve the problem of ringing in an emitter follower circuit by a careful individual design of the transistors and reducing their biasing currents. The technique described, however, has the disadvantage of decreasing pulse steepness.
What is needed is a way to solve the problem of ringing for a emitter/source follower circuit when the circuit has a capacitive load so that such a circuit may be used in an application such as a clock buffer. In addition, it is important that such a solution not cause other problems such as drawing too much current or slower rising and falling transition times.